The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a plurality of bank groups each having a plurality of banks sharing a global line group.
Generally, a semiconductor memory device is used for storing data and outputting desired data among the stored data. In other words, the operations of the semiconductor memory device include a write operation of storing data inputted from an external circuit and a read operation of outputting a stored data to an external circuit.
Generally, semiconductor memory devices such as a Dynamic random access memory (DRAM), one of volatile memory devices, use a memory cell for storing data. The semiconductor memory devices perform a sequence of operations such as an active operation, a read/write operation, and a precharge operation to store external data in the memory cell or output a stored data to an external circuit.
The active operation and the read/write operation are to select a designated cell from a plurality of DRAM cells and output a data stored in the selected cell or stores an external data therein. The precharge operation is to reset the DRAM to a state prior to the active operation.
Therefore, the semiconductor memory device must ensure time margins for the active operation, the read/write operation and the precharge operation so as to output the stored data or store the external data one time.
The semiconductor memory device includes a plurality of banks each being defined by grouping a plurality of cells. In order for more efficient data input/output operations, the banks are configured to independently input/output data.
FIG. 1 is block diagram of a conventional semiconductor memory device with a plurality of banks.
Referring to FIG. 1, the conventional semiconductor memory device includes a plurality of banks BANK0, BANK1, BANK2 and BANK3, a plurality of global input/output (I/O) lines GIO, a data input unit 130, and a data output unit 150. The banks BANK0, BANK1, BANK2 and BANK3 share the global I/O lines GIO and input and output data therethrough. The data input unit 130 transfers external data INPUT_DATA to the global I/O lines GIO, and the data output unit 150 outputs data IN_DATA applied on the global I/O lines GIO to an external circuit.
In such a semiconductor memory device, when one bank performs a read or write operation after an active operation, another bank performs an active operation and other bank performs a precharge operation. In this way, the banks perform the active operation, the read or write operation, and the precharge operation in turn.
In view of the data input/output timing between the semiconductor memory device and external circuits, data can be successively inputted or outputted in predetermined intervals. Thus, the data can be inputted or outputted at higher speed, compared with data of a semiconductor memory device that do not use the banks.
However, the data input/output operation using the banks needs a waiting time for the following reasons.
For example, in order to output data stored in the bank BANK0 to an external circuit, data stored at positions designated in the bank BANK0 are transferred to the global I/O lines GIO through the read operation and then are outputted through the data output unit 150 to the external circuit.
On the contrary, in order to store external data in the bank BANK0, the external data are transferred through the data input unit 130 to the global I/O lines GIO and then are stored in positions designated in the bank BANK0 through the write operation.
That is, in the read or write operation, data always pass through the data input unit 130, the data output unit 150, and the global I/O lines GIO.
Such a read or write operation is also applied on the first to third banks BANK1, BANK2 and BANK3. That is, in the read or write operation of the first to third banks BANK1, BANK2 and BANK3, data pass through the data input unit 130, the data output unit 150, and the global I/O lines GIO. Consequently, when one bank performs the read or write operation, the remaining banks cannot perform the read or write operation.
To solve the problem, a semiconductor memory device with a following modified structure was proposed.
FIG. 2 is a block diagram of a conventional semiconductor memory device with a plurality of bank groups.
Referring to FIG. 2, the conventional semiconductor memory device includes a plurality of bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3, a data input unit 220, a data output unit 240, data transfer units 280 and 290. Each of the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3 includes a plurality of banks BANK0, BANK1, BANK2 and BANK3. The banks BANK0, BANK1, BANK2 and BANK3 share one of global I/O line groups GIO_GRP0, GIO_GRP1, GIO_GRP2 and GIO_GRP3. The data input unit 220 transfers external data INPUT_DATA to data input global lines GIOW<0:1> and GIOW<2:3> in response to write commands WR_CMD<0:3> corresponding to the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3. The data output unit 240 outputs data applied on data output global lines GIOR<0:1> and GIOR<2:3> to an external circuit in response to read commands RD_CMD<0:3> corresponding to the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3. The data transfer units 280 and 290 transfer data applied on the global I/O line groups GIO_GRP0, GIO_GRP1, GIO_GRP2 and GIO_GRP3 to the data input global lines GIOW<0:1> and GIOW<2:3> or transfers data applied on the data output global lines GIOR<0:1> and GIOR<2:3> to the global I/O line groups GIO_GRP0, GIO_GRP1, GROUP_2 and GROUP_3. The semiconductor memory device may further include a command decoding unit 260 configured to decode external commands CMD and addresses ADDR to generate the write commands WR_CMD<0:3> and the read commands RD_CMD<0:3>.
An operation of the conventional semiconductor memory device with the plurality of bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3 will be described below.
The global I/O line group GIO_GRP0, GIO_GRP1, GIO_GRP2 and GIO_GRP3, the independent data input global lines GIOW<0:1> and GIOW<2:3>, and the independent data output global lines GIOR<0:1> and GIOR<2:3> can be independently provided for an input or an output operation in the respective bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3. Thus, the data can be immediately inputted or outputted at the substantially same time when the bank groups GROUP_0, GROUP_1, GROUP2 and GROUP_3 are all enabled. The substantially same time means 1 tCK, i.e., one period of a system clock (CLK), representing a minimum time interval necessary for the input of the external address to activate one bank group
When one of the bank groups is enabled, one of the plurality of banks BANK0, BANK1, BANK2 and BANK3 provided within the enabled bank group is enabled to output the data to the external circuit or store the external data.
Since the plurality of banks BANK0, BANK1, BANK2 and BANK3 within the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP3 can perform the active operation, the read/write operations, and the precharge operation in turn, the data can be immediately inputted or outputted even though a plurality of banks each included in one of the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3 are successively enabled at the substantially same time.
However, the line number of each of the global I/O line groups GIO_GRP0, GIO_GRP1, GIO_GRP2 and GIO_GRP3 is 64, the number of each of the data input global lines GIOW<0:1> and GIOW<2:3> is 128, and the number of each of the data output global lines GIOR<0:1> and GIOR<2:3> is 128. That is, in order for the bank groups GROUP_0, GROUP_1, GROUP_2 and GROUP_3 to perform data I/O operations independently, the group global I/O lines GIO_GRP0, GIO_GRP1, GIO_GRP2 and GIO_GRP3, the data input global lines GIOW<0:1> and GIOW<2:3>, and the data output global lines GIOR<0:1> are connected to one another in one-to-one way.
Such a configuration having two times the number of lines increases an area of the semiconductor memory device.